Presentation - Research and Development Driving Advanced Semiconductor Devices Challenging the End of the Roadmap
Semiconductor technology has known an exponential evolution in the last decades and is fully integrated in our everyday life. The global semiconductor industry sales are expected to reach about US$ 600 billion in 2024. This could only be achieved by the implementation of novel materials, advanced design concepts and new transistor architectures.
Research and development have focused on increased device performance and reduced power consumption, while maintaining a good manufacturability and yield performance without penalizing the cost/function. Device architectures such as FinFETs, TFETs, Gate-All-Around, nanowires (NWs), nanosheets (NSs) in both horizontal or vertical configurations, Forksheet and CFET structures are investigated enabling System-on-Chip (SoC) applications. In addition, the huge progress achieved in silicon technology and the heterogenous integration of Ge and III-V technologies on a silicon platform enables the on-chip integration of building blocks with different functionality.
Depending on the required power output, maximum breakdown voltage and frequency performance there is completion between SiC and GaN based technologies for a variety of applications fields such as mobile communication, automotive, consumer products, etc. The main challenges related to the hetero epitaxy of III-V materials on a Si substrate is the control of extended defects due to the lattice mismatch of the different materials.
Complex and dense SoC applications can be realized by 3D wafer stacking using Through-Silicon-Vias (TSV) for wafer-to-wafer bonding. The 3D integration results in a reduction of the RC product and interconnect length, a smaller form factor and enables vertical partitioning. Very promising results are also obtained for monolithic sequential 3D (S3D) processing based on the processing of different tiers on top of each other.
Major trends in above mentioned process integration approaches are reviewed and technological challenges of some process modules and device structures highlighted.
Biography - Cor Claeys
Cor Claeys is Professor at the KU Leuven (Belgium) since 1990. He was with imec, Leuven, Belgium from 1984 till 2016. His main interests are semiconductor technology, device physics, low frequency noise phenomena, radiation effects and defect engineering. He teaches several short courses in different parts of the world.
He co-edited books on “Low Temperature Electronics” and “Germanium-Based Technologies: From Materials to Devices” and wrote monographs on “Radiation Effects in Advanced Semiconductor Materials and Devices”, “Fundamental and Technological Aspects of Extended Defects in Germanium”, “Random Telegraph Signals in Semiconductor Devices” and “Metals in Silicon- and Germanium-Based Technologies: Origin, Characterization, Control and Electrical Impact”.
He also (co)authored 16 book chapters, over 1200 conference presentations and more than 1400 technical papers. He is editor/co-editor of 70 Conference Proceedings.
Prof. Claeys is a Fellow of the Electrochemical Society and of IEEE. He was EDS President in 2008-2009 and Division Director on the IEEE Board of Directors in 2012-2013. He is a recipient of the IEEE Third Millennium Medal and received the IEEE EDS Distinguished Service Award.
