Abstract

The cornerstone of the Internet of Things (IoT) paradigm is the availability of low-cost devices with ultra-low power wireless communication capabilities. Recently, the integration of artificial intelligence (AI) in IoT applications has emerged as a significant breakthrough for enhancing circuit performance. However, current solutions predominantly rely on cloud-based AI, which is power-intensive, dependent on internet connectivity, and unsuitable for real-time applications. Hardware-based AI is a promising alternative, offering potential for miniaturized and low-cost AI implementations. This tutorial provides a comprehensive overview of emerging neuromorphic circuits, encompassing both digital and analog solutions. The tutorial delves into literature and design considerations to illustrate energy-efficient edge AI solutions.

Bio

Pietro M. FERREIRA (IEEE S'03-SG'06-M'12-SM'18) received the B.Eng. cum lauda in Electronics and Computer Eng. in 2006, the M.Sc. in Microelectronics in 2008 from the Federal University of Rio de Janeiro (UFRJ), Brazil, the Ph.D. degree in Communications and Electronics in 2011 from the Télécom Paris (IPP), France, and Research Direction Diploma (HDR) in Physics in 2019 from the Université Paris-Saclay, France. Researching high-performance high-reliability circuits and systems, he joined IM2NP lab. (UMR CNRS 7334) for one year and IEMN lab. (UMR CNRS 8520) for two years during his tenure track. From 2014 to 2024, he was Associate Professor at Université Paris-Saclay, CentraleSupélec, GeePs (UMR 8507), France.  His research interests are design methodologies and microwave instrumentation techniques for ultra-low power integrated circuits in harsh environments. Recent projects aim the Internet of Things industry considering IA-edge and reliability.

Abstract

Contrarily to synchronous digital circuits, asynchronous circuits are considered difficult to design. This is probably due to a lack of designer knowledge and to a large variety of asynchronous designs. For instance, asynchronous quasi-delay insensitive circuits are by nature very different from synchronous circuits, which make them difficult to understand by non-skilled people. In contrast, asynchronous bundled-data circuits share a similar data-path with the synchronous circuits and a controller, ensuring the data propagation through the circuit, replaces the synchronization mechanism, namely the clock-tree. Therefore, designing bundled-data circuits is not at all a nightmare for synchronous designers because they can use their standard EDA tools with a little bit different strategy. This tutorial, after an introduction to asynchronous circuits, will show the path to establish a design flow for bundled-data circuits.

Bio

Laurent Fesquet (M’99-SM’09) received the M. Eng. Degree in physics from the Ecole Nationale Superieure de Physique, Strasbourg, France, in 1993, the M.S. Degree in applied physics from the Ecole Normale Superieure, Cachan, France, in 1994, and the Ph.D. degree in electrical engineering from Paul Sabatier University, Toulouse, France, in 1997. In 1999, he joined the Grenoble Institute of Technology, Grenoble, France, as an Associate Professor. He is currently the Deputy Director of CIME Nanotech, an academic center that supports microelectronic teaching and research activities and the Deputy Director of the TIMA laboratory. His research includes asynchronous circuit design, computer-aided design (CAD) tools, and non-uniform signal processing applied to several fields such as low power, security or RF.

Abstract

RISC-V is revolutionizing the technological landscape as the open standard Instruction Set Architecture (ISA). This session will delve into the current state of RISC-V, exploring its impact across various sectors, from the Internet of Things (IoT) to space exploration. Attendees will gain insights into the latest advancements and hot development areas within the RISC-V ecosystem, uncovering significant opportunities for research and development. We will also guide you on how to become a part of RISC-V International and collaborate on a global scale. Join us to explore how RISC-V is shaping the future of technology.

Bio

Rafael Sene is a seasoned Senior Software Engineer and Technical Program Manager at RISC-V International, where he works on advancing the development of the open standard ISA, RISC-V. With a distinguished career at IBM, Rafael has brought his extensive experience and expertise to drive the expansion of RISC-V in Latin America. His work focuses on fostering innovation and collaboration within the RISC-V community, supporting developers and organizations to harness the full potential of this groundbreaking technology. Rafael is dedicated to promoting RISC-V's mission of openness and inclusivity, ensuring its positive impact across diverse technological domains.

Abstract

The evolution of semiconductor devices has been responsible for a technological revolution, which changes the way we work, live and play. The real electronic revolution begins with the integration of transistors and other semiconductor devices into integrated circuits, nowadays present in everything around us. In this tutorial, the transistor evolution will be presented considering the differences in architectures, transport mechanisms and materials used in their fabrication. The analysis will be carried out based on the general electrical characterization of the devices, highlighting their potential for analog applications and finalizing with the design of basic and frequent analog blocks of integrated circuits using advanced transistors. Two different basic analog blocks will be presented: two-stage Operational Transconductance Amplifiers (OTA) and Low dropout voltage regulators (LDO) when designed with advanced devices like FinFETs, Tunnel-FETs, Ω-gate nanowires, nanosheets transistors and Vertical-FETs.

Bio

Paula Ghedini Der Agopian Paula Ghedini Der Agopian received the M.S. and Ph.D. degrees in microelectronics from the University of Sao Paulo (USP), São Paulo, Brazil, in 2003 and 2008. She was a Post-Doctoral Researcher with USP/Imec (Brazil/Belgium). She has been involved in the electrical characterization and simulation of transistors in advanced CMOS compatible technologies, mainly for analog applications. From 2004 to 2014, she was assistant Professor of Electrical Engineering with FEI University. From 2014 to 2016 she managed the Training Center for Integrated Circuit Designers at the Polytechnic School of USP under the CI-Brasil program. Since 2016, she has also been a Professor with UNESP, Sao Paulo State University. She is a senior member of IEEE and Chapter chair of the Electron Devices Society (EDS) of the IEEE of the South-Brazil Section. 

Abstract

AI applications span the IoT-Cloud continuum, integrating IoT, edge, and cloud computing to create seamless, intelligent systems. At the IoT level, sensors and devices collect real-time data, while edge computing processes it locally to reduce latency and bandwidth use. This local processing enables quick decision-making for time-sensitive applications, such as autonomous vehicle reactions, emergency responses in smart city infrastructure, healthcare monitoring, environmental adjustments in smart homes, and more. Further processing and deeper analysis occur in the cloud, where powerful AI models leverage vast data stores and computing resources for complex analyses and optimizations.

Considering that this complex AI continuum demands powerful hardware, this tutorial introduces the concepts of AI hardware for IoT, edge, and their interaction with the cloud, discussing non-functional requirements like latency, quality, power, energy, cost, etc. The tutorial covers the basics of AI execution hardware and their trade-offs: CPUs are versatile but slower; GPUs accelerate parallel tasks but consume more power; TPUs are energy efficient but less flexible, while FPGAs offer high performance and low energy but at higher design complexity. The tutorial also explores the trade-offs provided by different hardware options concerning the requirements above, which will vary depending on where execution takes place within the IoT-Cloud continuum. Lastly, the tutorial delves into optimization techniques and the exploitation of parallelism, covering specific network model optimizations, such as quantization, pruning, and early exit strategies, illustrated through practical case studies.

Bio

Antonio Carlos Schneider Beck Filho graduated in Computer Science from the Federal University of Santa Maria (UFSM) in 2002. He holds a master's degree (2004) and a PhD (2008) in Computer Science from the Federal University of Rio Grande do Sul (UFRGS), with a research internship at TUDelft, Netherlands, where he was also a visiting researcher in 2015. Currently, he is an Associate Professor at the Institute of Informatics at UFRGS and contributes to two graduate programs: PPGC and PGMicro. His research interests include reconfigurable systems, computer architectures, multicore processing, and AI hardware. He has authored over 150 articles in international conferences and journals, with extensive international and local collaboration, and has published three books. In recent years, he has received best paper awards at Computing Frontiers 2018, SBAC-PAD 2019, HPCC 2020, and PDP 2023, and awards for best PhD thesis supervision from the Brazilian Computer Association in 2020, and at SBAC/WSCAD 2019 and 2020, along with other honorable mentions and nominations. Antonio has also served on the technical program committees of several conferences, including DATE, ICCD, FPL, DSD, SBAC-PAD, SBCCI, ICECS, IESS, HEART, and ARC. For more information, visit www.inf.ufrgs.br/~caco.

Abstract

Superconducting quantum computing is a dynamically evolving field that leverages Josephson-junction-based qubits and superconducting circuits as scalable solutions for quantum information processing. Significant advancements have been made in the design and manufacturing of qubits, positioning them as foundational elements for some of the most promising approaches in quantum computing. This lecture provides a comprehensive overview of superconducting circuits, detailing the fundamental physics that underpins them and discussing current research trends and applications within Brazil. Attendees, from students and researchers to technology enthusiasts, will develop a fundamental understanding of this cutting-edge technology. Additionally, the lecture will delve into emerging technologies in quantum processing, communication, and simulation, providing a broad perspective on the potential and direction of quantum technologies.

Bio

Francisco Paulo Marques Rouxinol received his B.Sc., M.Sc., and Ph.D. degrees in Physics from the Universidade Estadual de Campinas (UNICAMP), Brazil, completing his doctoral studies in 2008 with a focus on magnetic properties of thin films. He then pursued postdoctoral research at Syracuse University, NY, USA, from 2010 to 2015, supported by The National Science Foundation, where he advanced his expertise in quantum circuits and nanomechanical systems. Dr. Rouxinol is currently a Professor at UNICAMP’s Institute of Physics Gleb Wataghin, specializing in the fields of quantum circuit electrodynamics, superconducting devices, and nanomechanics. Dr. Rouxinol's research interests include the development of hardware and software for low-noise measurements at RF/microwave frequencies and the integration of novel quantum devices. His significant contributions span both theoretical and experimental physics, with a particular focus on quantum measurements, qubit-resonator systems, and hybrid quantum systems. His work has led to innovative approaches in quantum sensing and the manipulation of quantum states, enriching the understanding of quantum coherence and entanglement in macroscopic systems.Throughout his career, Dr. Rouxinol has been involved in several high-impact projects, including leading roles in projects aimed at developing new microelectronic devices and processes for quantum computing applications. He has collaborated extensively with international research groups and industries, enhancing the practical applications of quantum technologies. Dr. Rouxinol has published numerous articles in prestigious journals and has been an active member of the scientific community, serving as a reviewer for several high-profile scientific journals and as a member of various academic committees.